(a) Fields of the Invention
The present invention relates to semiconductor devices and methods for fabricating the same.
(b) Description of Related Art
In a recent semiconductor device field, speed enhancement and power consumption reduction of semiconductor devices due to rapid miniaturization of the devices have proceeded. Accompanied with such a trend, gate insulating films of transistors in the devices have become thinner, and diffusion profiles therein have been changed considerably. This makes it difficult to ensure the reliability of the device.
FIGS. 5A to 5E are sectional views showing steps of a conventional fabrication method of a semiconductor device. In FIGS. 5A to 5E, an n-channel MIS transistor for an internal circuit (internal MIS Tr) is formed in an internal circuit area AreaA illustrated in the left halves of these figures, and an n-channel MIS transistor for a peripheral circuit (peripheral MIS Tr) is formed in a peripheral circuit area AreaB illustrated in the right halves of these figures.
In the conventional fabrication method of a semiconductor device, first, in the step shown in FIG. 5A, in a p-type semiconductor region (referring to part of a semiconductor substrate) 111, regions surrounding an active region 110a and an active region 110b are formed with isolation regions 112, respectively, by a normal shallow trench isolation process. Thereafter, a gate insulating film 113a and a gate electrode 114a are formed above the active region 110a of the internal circuit area AreaA, and a gate insulating film 113b and a gate electrode 114b are formed above the active region 110b of the peripheral circuit area AreaB.
Next, in the step shown in FIG. 5B, on a substrate, an implantation mask 115 of photoresist is formed which covers the internal circuit area AreaA and has an opening in the peripheral circuit area AreaB. Thereafter, with the implantation mask 115 covering the internal circuit area AreaA, arsenic ions serving as an n-type dopant are implanted using the gate electrode 114b as a mask to form n-type extension regions 116 in regions of the active region 110b of the peripheral circuit area AreaB located below both sides of the gate electrode 114b, respectively.
Subsequently, in the step shown in FIG. 5C, the implantation mask 115 is removed, and an implantation mask 117 of photoresist is formed which covers the peripheral circuit area AreaB and has an opening exposing the internal circuit area AreaA. Thereafter, with the implantation mask 117 covering the peripheral circuit area AreaB, arsenic ions serving as an n-type dopant are implanted using the gate electrode 114a as a mask to form n-type extension regions 119 in regions of the active region 110a of the internal circuit area AreaA located below both sides of the gate electrode 114a, respectively. While the implantation mask 117 used in the formation of the n-type extension regions 119 is left remaining, boron ions as a p-type dopant are implanted using the gate electrode 114a as a mask to form p-type pocket regions 118 in the active region 110a of the internal circuit area AreaA.
Next, in the step shown in FIG. 5D, the implantation mask 117 is removed, and an insulating film (not shown) covering top and side surfaces of the gate electrodes 114a and 114b is formed on the substrate. Thereafter, the insulating film is etched back to form insulating sidewalls 120a on the side surfaces of the gate electrode 114a of the internal circuit area AreaA and insulating sidewalls 120b on the side surfaces of the gate electrode 114b of the peripheral circuit area AreaB.
Then, in the step shown in FIG. 5E, ion implantation of an n-type dopant is conducted using the gate electrode 114a, the insulating sidewalls 120a, the gate electrode 114b, and the insulating sidewalls 120b as a mask, thereby forming n-type source and drain regions 121a in the active region 110a of the internal circuit area AreaA and n-type source and drain regions 121b in the active region 110b of the peripheral circuit area AreaB.
In past years, a gate insulating film of a MIS transistor was sufficiently thick, so that the hot carrier lifetime which is important as the reliability of the MIS transistor was able to be ensured easily. In addition, source and drain regions thereof were formed without complication by forming a gate electrode, implanting arsenic ions, phosphorus ions, or the both ions using the gate electrode as a mask, and then performing annealing. However, since, in recent years, rapid miniaturization of the semiconductor devices has proceeded, the gate insulating film has been thinned and the dopant concentrations of source and drain required to ensure current have been increased, resulting in a rise in the electric field intensity of a channel in the device. Therefore, in the structure of the device as described above, hot carriers are likely to occur around the edge of the drain, and thus the reliability of the transistor is disadvantageously lowered.
To solve this disadvantage, a method for improving hot carrier resistance by nitrogen ion implantation has been studied. For example, Japanese Unexamined Patent Publication No. H09-64362 proposes a method for improving resistance to hot carrier degradation. In this method, a gate oxide film and a gate electrode of polysilicon are formed above a semiconductor substrate, and then nitrogen ions are implanted by oblique rotating ion implantation to change portions of the gate oxide film immediately below edges of the gate electrode to nitrided oxide films (oxynitride films). A subsequent ion implantation forms source and drain regions in the semiconductor substrate, thereby improving resistance to hot carrier degradation.
Japanese Unexamined Patent Publication No. H09-64362 also proposes another method for improving resistance to hot carrier degradation. In this method, a silicon oxide film is formed on the entire surface of a semiconductor region with a gate oxide film and a gate electrode provided thereabove, and then nitrogen ions are implanted on the condition in which the peak of the implantation profile appears around the interface between the silicon oxide film and the silicon substrate. The resulting silicon oxide film is etched back to form sidewalls on side surfaces of the gate electrode, and a subsequent ion implantation forms source and drain regions in the semiconductor region, thereby improving resistance to hot carrier degradation.
However, even the methods mentioned above cannot fully deal with rapid miniaturization of semiconductor devices. As a consequence, it is increasingly difficult to ensure a sufficient hot carrier lifetime of the device. In addition, when nitrogen is directly implanted into the gate oxide film as shown in the method proposed by Japanese Unexamined Patent Publication No. H09-64362, the reliability of the oxide film itself is disadvantageously lowered.